1. Field of the Invention
The present invention relates to a semiconductor integrated circuit module and a semiconductor integrated circuit device stacking the same which are used in digital computers such as workstations, personal computers or the like. Particularly, the present invention relates to a semiconductor integrated circuit module in which a plurality of monolithic bare IC chips or a plurality of TAB packages are mounted, and a semiconductor integrated circuit device in which a plurality of the same are stacked.
2. Description of the Related Art
In digital computers, semiconductor integrated circuit devices are usually used in which IC chips are mounted on a printed circuit board by soldering. Hereinafter, a conventional semiconductor integrated circuit device is described by way of explaining an internal memory circuit as an example.
FIG. 1 is a perspective view illustrating an example of such a conventional internal memory circuit. Four memory ICs 11a-11d are mounted on a printed circuit board 14. The printed circuit board 14 is a four-layered Cu-clad board which has a base sheet made of a glass textile soaked with an epoxy resin. The printed circuit board 14 is provided with signal wirings such as an address bus and a data bus (not shown in FIG. 1, see FIG. 2) on both the top and the bottom faces thereof, and with a power source line and a ground line being installed inside the printed circuit board 14.
These memory ICs 11a-11d are generally fabricated in a package structure, which is formed in the following manner. First, bare IC chips with a monolithic structure are electrically connected to lead frames 15a-15d by a die bonding technique and a wire bonding technique. Then, the entire structure is encapsulated with a resin material so as to be packaged. The memory ICs 11a-11d thus fabricated are surface-mounted on the printed circuit board 14 by soldering the lead frames 15a-15d to external circuits such as signal wirings on the printed circuit board 14.
FIG. 2 shows-an example of a circuit diagram of the internal memory circuit.
The memory ICs 11a-11d may typically be DRAMs. An address bus 12 and a data bus 13 are connected to each of the memory ICs 11a-11d. In addition, a group of signal lines 16 comprising a power source line Vss, a ground line GND, row address strobe signal lines (hereinafter, referred to as /RAS signal lines) /RAS-1 to /RAS-4, column address strobe signal lines (hereinafter, referred to as /CAS signal lines) /CAS-1 to /CAS-4, a write enable signal line (hereinafter, referred to as a /WE signal line) /WE and an output enable signal line (hereinafter, referred to as an /OE signal line) /OE is connected to each of the memory ICs 11a-11d.
As seen in FIG. 2, each of the memory ICs 11a-11d has one of the /RAS signal lines and one of the /CAS signal lines connected thereto. This is because the /RAS signal and the /CAS signal are signals to be input to each of the memory ICs 11a-11d for selecting one of them to be accessed. In order to access a particular memory IC, the /RAS signal and the /CAS signal are input selectively thereto. Furthermore, during an access operation, data is written in the memory IC upon receiving the /WE signal and recorded data is read from the memory IC upon receiving the /OE signal.
Meanwhile, one of strongly desired requirements of digital computers these days is an increase in the processing speed. One of the approaches to meet this requirement is to increase the memory capacity of the internal memory installed therein. The number of accesses to an external memory and the required time for the accessing procedure can be reduced by providing an internal memory with a large capacity, which makes it possible to achieve a higher processing speed.
In order to increase the memory capacity of the internal memory circuit, a number of memory ICs great enough to satisfy the requirement must be mounted on the printed circuit board 14. However, in the conventional internal memory circuit as shown in FIG. 1 wherein the memory ICs 11a-11d are surface-mounted on the printed circuit board 14 in one layer, increasing the number of memory ICs to be mounted on the printed circuit board leads to such problems as described below.
(1) Wirings connected to each of the memory ICs become longer, resulting in a greater wiring impedance. As a result, transmission characteristics of signals deteriorate, which makes high speed processing difficult.
(2) Increased length of the wirings further causes reflection of the signals at the terminating end of the wirings. Reflected signals distort the original signal waveforms which are propagating in the wirings. In FIG. 2, for example, the memory IC 11a connected to the signal wiring near the starting end thereof and the memory IC 11d connected to the wirings near the terminating end thereof have different access timings as well as input signals with different waveforms because of the interference with the reflected signals. To ensure reliable operations of the internal memory circuit under such conditions, the access timing margin must be increased. Consequently, high speed processing becomes difficult.
(3) As the number of the memory ICs to be mounted increases, a larger area of the printed circuit board 14 is required. Thus, an increased size of the apparatus is needed. Moreover, because the four-layered Cu-clad circuit board is relatively expensive, increasing the circuit board area means an increase in costs.
To help overcome The above problems, a multi-layered integrated memory circuit has been proposed wherein a plurality of memory IC chips or a plurality of memory modules which include a plurality of memory IC chips are stacked in layers on top of each other. Such a multi-layered integrated memory circuit can solve the space problems of the conventional surface-mounted memory circuits to a large extent.
However, new problems relating to the method of connecting the lead frame arise.
As described previously, each memory IC is provided with the address bus 12, the data bus 13 and the group of the signal lines 16 being connected thereto. On the other hand, in the conventional multilayered memory circuits, memory chips or memory modules are stacked while arranged in the same direction. Each of lead terminals which are located at corresponding locations in the lead frames of each of the memory chips or the memory modules is connected to each other and further connected to the same terminal pad on the printed circuit board. In such a case, a signal given to one lead terminal via one terminal pad is transmitted through the connected lead frames to all of the memory ICs or the memory modules in every layer of the multi-layered integrated memory circuit.
No problem related to the signal transmission arises even in such a wiring architecture as far as the terminals of the signals to be connected commonly to each memory IC are involved. On the other hand, the /RAS signal and the /CAS signal cannot be selectively transmitted to one particular layer in the multilayered structure of the above-mentioned simple stacking structure.
In order to solve the problem, such an arrangement requires the /RAS signal terminals and the /CAS signal terminals to be arranged at different positions in advance, depending on which layer the particular memory IC is to be mounted in. For example, The Japanese Laid-open Patent Publication No. 4-26152 and the U.S. Pat. No. 4,982,265 disclose the multilayered integrated memory circuits wherein memory IC chips having different configurations or arrangements of lead terminals are stacked in each layer.
However, such a circuit architecture suffers a disadvantage in that several kinds of the memory IC chips having different configurations and arrangements of the lead terminals must be manufactured depending on which layer they are to be mounted in. This may bring about an increase in the manufacturing costs.
In addition, with such an arrangement of the terminals, an additional manufacturing step must be conducted before the mounting process so as to check if the memory ICs to be mounted in each layer have the proper terminal arrangement as designated in the design and to reject improper memory IC chips. When the memory IC chips have been already encapsulated in a plastic package structure, the wirings inside the package cannot be checked visually and therefore must be checked in other ways, such as by means of electrical conduction test or the like. This may also cause the manufacturing costs to increase.
Japanese Patent Publication No. 5-14427 discloses another multi-layered integrated memory circuit capable of solving the above-mentioned problems to some extent. In the multi-layered integrated memory circuit device, independent lead terminals for selecting the IC chips to be accessed are formed in a branched shape in the outer lead portion in a number corresponding to the number of chips to be stacked, while remaining unseparated in the inner lead portion.
The independent lead terminals with such features make it possible to mass-produce the memory IC chips having the same structure in the same process irrespective of which layer they are to be mounted in. During the mounting process, all of the branches except one branch in the outer lead portion of the independent lead terminals are cut off, depending on which layer the chip is to be mounted in. This configuration makes it possible that signals can be transmitted selectively only to the memory IC chips or the memory modules in a particular layer.
However, in the above structure, a new step of fabrication, i.e. cutting off the unnecessary branches in outer leads, must be added. Thus, it still has points to be solved so as to improve the manufacturing efficiency and to reduce costs.